The present invention is in the field of integrated circuit networks and more particularly is directed to charge domain parallel processing networks.
Vector-matrix product processing systems are generally known in the art. By way of example, U.S. Pat. No. 4,464,726 discloses a particularly effective form of such systems. That patent discloses a charge domain vector-matrix product system including a floating gate tapped delay line for holding and shifting analog sampled-data in the form of charge packets, and including an array (or a matrix) of charge coupled device (CCD) digital-analog multipliers, for example, in the form disclosed in the U.S. Pat. No. 4,458,324, referred to as multiplying digital-to-analog converters (MDAC's). At each stage of the delay line there is a floating-gate sensing electrode. The output of the sensing electrode is coupled to the analog input port of a corresponding CCD digital-analog multiplier. The output of each multiplier is a charge packet which is proportional to the product of the analog sampled data and a digital word.
This structure can be used to form networks adapted for performing high level mathematical operations such as vector-matrix product, i.e., ##EQU1## for k=1, 2 . . . K.
In the disclosure of U.S. Pat. No. 4,464,726, the digital words c.sub.nk for the MDAC's (i.e., the matrix values) are provided by an N.times.K.times.M-bit, parallel-addressable, digital memory, which may be on-chip or off-chip, and may be CCD or ROM, in either volatile or non-volatile form.
Such vector-matrix product networks may be configured to perform functions such as discrete fourier transforms (DFT). In alternate configurations, the network may eliminate scanning round clutter from an aircraft surveillance radar by performing as an optimal moving target indicator (MTI) filter bank. In yet other configurations, the network may function as a matched filter bank for applications such as the Global Positioning System (GPS).
An important limitation for the prior art charge domain vector-matrix product processing systems is that only a single set of matrix values may be readily stored and be readily accessible for the system, although that storage is programmable (an important advantage) to permit re-programming after a product operation with a different set of matrix values. As a result of this limitation, certain applications which require a rapid succession of vector-matrix product computations must use multiple networks, operating in parallel, each performing a single vector-matrix product computation. Alternatively, the time required for such operations is limited by the loading (i.e., programming) time for the matrix values.
It is an object of the present invention to provide an improved charge domain parallel processing network.
It is another object to provide an improved charge domain vector-matrix product processing system.
Another object is to provide a vector-matrix product processing system adapted to perform rapid successive vector-matrix product computations.